The present invention relates to a synchronous DRAM (SDRAM). More particularly, the present invention relates to an SDRAM having a column access strobe (CAS) latency, as well as a method for controlling the CAS latency.
In general, an SDRAM is synchronized with a clock signal input from outside the circuit and so the read or write operation of the SRAM is controlled. FIG. 13 describes the latency from the application of a row access command or a column access command to the output of data.
The number of clock cycles of an external clock signal from the application of a row access command to the output of first data is called the RAS latency (RL). The number of clock cycles of the external clock signal from the application of a column access command to the output of the first data is called the CAS latency (CL). The number of clock cycles of the external clock signal from the application of the row access command to the application of the column access command with respect to the same memory bank is called the RAS-CAS latency (RCL). The relationship between RCL, RL, and CL is shown in Equation 1. EQU RL=RCL+CL (1)
When the minimum value of the RAS latency in the frequency of a specific external clock signal is RL.sub.min, then RL must satisfy Equation 2. EQU RL.gtoreq.RL.sub.min (2)
When the minimum value of the CAS latency in the frequency of the specific external clock signal is CL.sub.min, then RCL.sub.min (the minimum RAS-CAS latency) is expressed as shown in Equation 3. EQU RCL.sub.min =RL.sub.min -CL.sub.min (3)
In a system using an SDRAM, a function of normally outputting data even when RCL&lt;RCL.sub.min, namely, in posted CAS latency, is required in order to improve the performance of the system. In this application, posted CAS latency refers to the fact that the CAS command comes earlier than the conventional RCL.sub.min. In other words,RL.gtoreq.RL.sub.min, which is generally the product specification, must be satisfied even when RCL&lt;RCL.sub.min. In order to satisfy the equality RL.gtoreq.RL.sub.min in the posted CAS latency, the CAS latency CL must satisfy Equation 4 EQU CL&gt;CL.sub.min +(RCL.sub.min -RCL) (4)
In a conventional SDRAM, since the specification of (RCL.sub.min -RCL)&lt;0 is required, it is enough to determine the CL, which guarantees the minimum CAS latency CL.sub.min by a mode register set (MRS) command. However, in a posted CAS state, it is possible to input a CAS command (including a column address command), which controls an appropriate delay time and the latency of a data path only when each of the values in Equation 4, i.e., (RCL.sub.min -RCL) and CL.sub.min, are known.